//////////////////////////////////////////////////////////////////////////////////
//                                                                              //
//                                                                              //
//  Author: lhj                                                                 //
//                                                                              //
//          ALINX(shanghai) Technology Co.,Ltd                                  //
//          heijin                                                              //
//     WEB: http://www.alinx.cn/                                                //
//     BBS: http://www.heijin.org/                                              //
//                                                                              //
//////////////////////////////////////////////////////////////////////////////////
//                                                                              //
// Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd                        //
//                    All rights reserved                                       //
//                                                                              //
// This source file may be used and distributed without restriction provided    //
// that this copyright statement is not removed from the file and that any      //
// derivative work contains the original copyright notice and the associated    //
// disclaimer.                                                                  //
//                                                                              //
//////////////////////////////////////////////////////////////////////////////////

//================================================================================
//  Revision History:
//  Date          By            Revision    Change Description
//--------------------------------------------------------------------------------
//2018/1/3                    1.0          Original
//2019/11/14                  1.1          Original
//*******************************************************************************/
module uart_test
(
input                            sys_clk,       //system clock 50Mhz on board
input                            rst_n,         //reset ,low active
input                            uart_rx,       //fpga receive data
output                           uart_tx        //fpga send data
);

parameter                        CLK_FRE = 50;//Mhz

wire [95:0] rx_data_out;
wire start;


wire signed [20:0] read_1;
wire signed [20:0] read_2;
wire signed [20:0] read_3;
wire signed [20:0] read_4;



wire valid2;
wire signed [20:0] out1;
wire signed [20:0] out2;
wire signed [20:0] out3;

reg    [7:0]   tx_data;
wire   tx_data_ready;   

reg [3:0]cnt;
reg tx_data_valid; 
               
assign rx_data_ready = 1'b1;//always can receive data,
							//if HELLO ALINX\r\n is being sent, the received data is discarded

assign read_1 = rx_data_out[20:0];
assign read_2 = rx_data_out[44:24];
assign read_3 = rx_data_out[68:48];
assign read_4 = rx_data_out[92:72];

ann2 ann2_inst(
    .clk             (sys_clk)          ,
    .rst_n           (rst_n)          ,
                        
    .ina             (read_1)          ,
    .inb             (read_2)          ,
    .inc             (read_3)          ,
    .ind             (read_4)          ,
    .valid_in        (start)          ,
                          
    .valid_out       (valid2)          ,
    .out1            (out1)          ,
    .out2            (out2)          ,
    .out3            (out3)          
);

always@(posedge sys_clk or negedge rst_n)begin
    if (!rst_n) begin
        tx_data<=8'd4;
    end
    else if(valid2) begin
       
	     if(out1>out2 && out1>out3)
		  tx_data <= 8'd0;
		  else if (out2>out1 && out2>out3)
		  tx_data <= 8'd1;
		  else if (out3>out1 && out3>out2)
		    tx_data <= 8'd2;
          else
            tx_data <= 8'd3; 
	end
	else
	    tx_data<=tx_data;
end

always@(posedge sys_clk or negedge rst_n)begin
    if (!rst_n) begin
        cnt<=4'd0;
    end
    else if(valid2)begin
       if(cnt<=4'd8)begin
        cnt<=cnt+1'd1;
        end
        else begin
          cnt <= cnt ;
        end
    end
end

always@(posedge sys_clk or negedge rst_n)begin
    if (!rst_n) begin
        tx_data_valid<=1'd0;
    end
    else if(cnt==4'd8)begin
        tx_data_valid<=1'd1;
    end
    else
         tx_data_valid<=1'd0;
end	   



uart_rx#
(
.CLK_FRE(CLK_FRE),
.BAUD_RATE(115200)
) uart_rx_inst
(
.clk                        (sys_clk                  ),
.rst_n                      (rst_n                    ),
.rx_data_out                    (rx_data_out                  ),
.start             (start            ),
.rx_data_ready              (rx_data_ready            ),
.rx_pin                     (uart_rx                  )
);

uart_tx#
(
.CLK_FRE(CLK_FRE),
.BAUD_RATE(115200)
) uart_tx_inst
(
.clk                        (sys_clk                  ),
.rst_n                      (rst_n                    ),
.tx_data                    (tx_data                  ),
.tx_data_valid              (tx_data_valid            ),
.tx_data_ready              (tx_data_ready            ),
.tx_pin                     (uart_tx                  )
);
endmodule